Given a 3-wide in-order processor, draw the optimal pipeline diagram and answer question 6-9, showing for each instruction, what stage of the pipeline it is in for each cycle for the execution of the code sequence below. Assume full bypassing of values from the respective instruction completion stage to the Decode stage. Assume that pipeline X can execute branches and ALU operations, pipeline Y can excute loads, stores, and ALU operations, and

6.
Question 6
Use the following architecture for questions 6-9:

Given a 3-wide in-order processor, draw the optimal pipeline diagram and answer question 6-9, showing for each instruction, what stage of the pipeline it is in for each cycle for the execution of the code sequence below. Assume full bypassing of values from the respective instruction completion stage to the Decode stage. Assume that pipeline X can execute branches and ALU operations, pipeline Y can excute loads, stores, and ALU operations, and

Code sequence for questions 6-9:

Which instructions stall due to data hazard? Check all that apply

4 points

  • 4: ADD R14, R11, R15
  • 7: LW R22, 4(R19)
  • 8: LW R24, 8(R19)
  • 10: LW R26, 16(R19)
  • 11: OR R11, R26, R18
  • 13: ADDIU R16, R17, 3